Kirin 9050 Pro: Inside Huawei’s Double-Die LogicFolding Chip

Huawei’s Kirin 9050 Pro is an engineering statement: a “double die” chip that stacks two layers of silicon on top of each other using copper-to-copper hybrid bonding, in a design Huawei calls LogicFolding. The chip powers the new Mate 90 Pro Max and Mate XT 2, and the Kirin 9050 Pro is shaping up to be one of the most talked-about mobile processors of the year.

The launch puts advanced chip packaging at the center of the smartphone race. Rather than waiting for a smaller transistor node, Huawei has gone vertical with the Kirin 9050 Pro, wiring two full dies together with tens of millions of vertical interconnects. It may be the most aggressive 3D chiplet design ever shipped in a consumer phone.

Huawei calls the approach LogicFolding, and the name is fitting: instead of folding more features onto a single flat die, the company has folded the chip itself, stacking logic over logic. The copper-to-copper hybrid bonding fuses the two dies at the atomic level, creating direct metal connections that are shorter, denser, and more power efficient than the solder bumps used in older stacked packages.

What Is the Kirin 9050 Pro’s Double-Die Design?

According to the teardown analysis highlighted by the X account TECHINFOSOCIALS, each of the two dies measures about 120.6 square millimeters, for a combined 241.3 square millimeters of silicon, roughly 70 percent more silicon area than the 141.7 square millimeter Kirin 9030 Pro. These are reported figures from the analysis and have not been independently verified.

The dies are joined by vertical copper-to-copper hybrid bonding at a reported 1.5 micrometer pitch, creating around 50 million vertical connections between the layers, according to the analysis. Through-silicon vias carry power and signals between the dies, and a reported 80,000 TSVs connect the chip to its substrate, taking up about 8 percent of the usable area, the analysis adds. The result is a single 3D chip that behaves like one large piece of silicon even though it is built from two.

What’s on Each Die of the Kirin 9050 Pro

The main die holds the computationally intensive blocks: CPU, GPU, NPU, DSP, ISP, memory controller, modem, SLC controller, and load/store, integer, and floating-point units. The secondary die is devoted to cache and I/O: L1, L2, and L3 caches including 12MB of SLC, plus LPDDR PHY, USB 3.2, RF interface, and PLL blocks.

Separating the hot, power-hungry compute logic from the area-heavy cache and I/O shortens electrical paths, which cuts latency and allows lower voltage and lower power consumption at the same frequency. In other words, the Kirin 9050 Pro does not just add more transistors. It rearranges them to use less energy per operation.

Kirin 9050 Pro Performance

Independent Geekbench 7 listings back up the flagship positioning. GSMArena reports a nine-core CPU with a prime ultra core at 3.1GHz scoring around 1,317 single-core and 5,381 multi-core aboard the Mate 90 Pro Max, while Notebookcheck recorded 1,117 and 5,076 with two cores at 2.75GHz and six efficiency cores at 1.60GHz. Bernstein Research, cited by GSMArena, describes SMIC 7nm-class N+2/N+3 process technology, and Wccftech’s die-shot coverage shows a compute die on the N+3 process bonded to an SRAM die on N+2.

The two sets of Geekbench figures suggest the Kirin 9050 Pro is being tested in more than one configuration, with clock speeds and core counts varying between listings. Even the lower of the two scores places the chip well clear of its predecessors and even the other 2nm competing chips, underlining how much of the Kirin 9050 Pro’s advantage comes from packaging rather than process.

Why LogicFolding Matters

With leading-edge process shrinks out of reach, Huawei is stacking transistors vertically instead, raising density and cutting power without a smaller node. It is the same workaround logic analysts have pointed to as Huawei’s answer to sanctions-era chip constraints.

The approach also mirrors where the wider semiconductor industry is headed. As transistor shrinks get more expensive, advanced packaging, from chiplets to 3D stacking, has become the industry’s main lever for performance gains. Huawei’s Kirin 9050 Pro simply pushes that lever further than any phone chip before it.

Whether LogicFolding becomes the template for future Kirin chips remains to be seen, but the Kirin 9050 Pro already stands as proof that Huawei’s silicon roadmap is advancing on a different axis from the rest of the industry. Expect rivals to be watching closely.

Sources: TECHINFOSOCIALS on X,